summarized. Introduction总结介绍.pdfVIP

ECS Transactions, 33 (3) 459-466 (2010) 10.1149/1.3481634 © The Electrochemical Society Atomic-Layer-Deposited High-k Dielectric Integration on Epitaxial Graphene P.D. Ye, A.T. Neal, T. Shen, J.J. Gu, M.L. Bolen, and M. A. Capano School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, U.S.A. The scaling of silicon-based MOSFET technology beyond the 22 nm node is challenging. Further progress requires new channel materials such as Ge, III-V semiconductors, carbon nanotubes (CNTs) and graphene. Perfect top-gate dielectric stacks are needed in order to sustain their potential device performance for carbon nanoelectronics. Due to the inert nature of carbon surfaces of CNTs and graphene, the challenges and current work on atomic- layer-deposited (ALD) high-k/CNTs and graphene integration are reviewed. The research work performed at Purdue University on ALD high-k integration on epitaxial graphene on SiC is summarized. Introduction The continuous device scaling and performance improvements required by the International Technology Roadmap of Semiconductors (ITRS) are facing a grand challenge as conventional Si CMOS scaling comes to its fundamental physical limits. As