基于FPGA电梯控制系统仿真图.docVIP

系统主体模块的设计与仿真附录A 电梯控制器总体框图 附录B 电梯控制器主体的程序 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity lift is port ( clk: in STD_LOGIC; --2hz信号 upin: in STD_LOGIC; --上升请求键 downin: in STD_LOGIC; --下降请求键 st_ch: in STD_LOGIC; --楼层选择键 close: in STD_LOGIC; --提前关门键 delay: in STD_LOGIC; --延时关门键 run_stop: in STD_LOGIC; --电梯运行开关 lamp: out STD_LOGIC; --运行或停止灯 run_wait: out STD_LOGIC_VECTOR (3 downto 0); --运行或等待时间 st_out: out STD_LOGIC_VECTOR (3 downto 0); --电梯所在楼层指示 direct: out STD_LOGIC_VECTOR (3 downto 0) --楼层选择指示 ); end lift; architecture rtl of lift is component led port(ledin:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0)); end component; signal ur,dr:STD_LOGIC_VECTOR (9 downto 1); signal dir,liftor:integer range 0 to 8; signal wai_t:STD_LOGIC_VECTOR (2 downto 0); signal divide,hand,clkin:STD_LOGIC; signal ladd:STD_LOGIC_VECTOR (1 downto 0); signal closex,delayx:STD_LOGIC; --signal run_wait: STD_LOGIC_VECTOR (3 downto 0); --signal st_out: STD_LOGIC_VECTOR (3 downto 0); --signal direct: STD_LOGIC_VECTOR (3 downto 0); begin direct=conv_std_logic_vector(dir,4)+1; st_out=conv_std_logic_vector(liftor,4)+1; run_wait=0wai_t; lamp=ladd(1); hand=wai_t(2) and (not wai_t(1)) and wai_t(0); closex=close and (not ladd(1)); delayx=delay and (not ladd(1)); --urun_wait:led port map(run_wait,run_waitdis); --ust_out:led port map(st_out,st_outdis); --udirect:led port map(direct,directdis); p0:process(clk) begin if (clkevent and clk=1) then clkin=not clkin; --lamp=ladd(1); end if; end process p0; --hand=wai_t(2) and (not wai_t(1)) and wai_t(0); --closex=close and (not ladd(1)); --delayx=delay and (not ladd(1)); p1:process(clkin) begin if (clkinevent and clkin=1) then divide=not divide; if (dir=8) then dir=0; else dir=dir+1; end if; end if; end process p1; p2:process(ur,dr,dir,upin,downin,st_ch,liftor,wai_t,run_stop,hand) variable num,t:integer range 0 to 9; begin num:=liftor+1; t:=dir+1