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43Gbs Differential TransimpedanceLimiting Amplifiers 43例格林巴利综合征鉴别阻限幅放大器课件
6-k?? 43-Gb/s Differential Transimpedance-Limiting Amplifiers with Auto-zero Feedback and High Dynamic Range Outline Overview Broadband low-noise amplifier topologies and design methodology Circuit design and features Measurement results Summary Low-noise broadband amplifier topology Goals Minimize noise when circuit operated as TIA with 60-fF photodiode and As 50-W voltage preamplifier Maximise dynamic range by using on-chip active feedback that does not degrade overall noise. Low-noise broadband topology choices EF-input stages have series feedback which increases noise impedance and results in very high noise figure. Noise figure topology analysis Diff. INV stage with on-chip 50 ??resistors?has low-to-moderate noise but poor broadband S11 F(Z0 = 50 W) = 1 + [1 + (wLF/Z0)2]-1 + GntZ0 + RntZ0(Ycort + 2/Z0)2 where: Gnt = G w2LEOPT, Ycort = jBwLEOPT and Rnt = R/LEOPT Diff. TIA stage matched to 50 ? offers lowest noise and broadband S11 matching F(Z0) = 1 + (Z0/RF)[1+(wLF/RF)2]-1 + GntZ0 + RntZ0(Ycort + 1/Z0 +1/RF )2 If RF=Z0 the two stages have identical Noise Figure. Transistor sizing for noise impedance Inverter input stage with matching 50-??resistors?has moderate transistor size (lEOPT) and bias current. lEOPT = [2/(wZ0)][R/(G + RB2)]1/2 TIA stage matched to 50 ? offers lowest size (since RF Z0) and bias current. lEOPT = (1/w)(1/RF + 1/Z0)][R/(G + RB2)]1/2 where R, G, B are technology-specific noise parameters TIALA specifications TIALA block diagram TIA stage schematics Peak detector and output stage DC auto-zero feedback stage Chip microphotograph Fabricated by HRL-Laboratories 1 ?m, 160-GHz InP/InGaAs HBT process Substrate height of 100 ?m Two metal layers MIM capacitors Metal resistors 70-? CPWs for isolation On-wafer DC output offset measurements Output differential DC-offset less than 40 mVpp for entire range of input DC current On-wafer S-parameter measurements TIA BW3dB 38 GHz TIA Tz gain 540 ? TIALA BW3dB 36 GHz TIALA S21 40 dB
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