CPC Capacitance measurementscpc电容测量.pptVIP

Status of Oxford Setup Matthew Chalk, Erik Devetak, Johan Fopma, Brian Hawes, Ben Jeffery, Nikhil Kundu, Andrei Nomerotski University of Oxford ( 18 August 2006 ) Oxford Test Setup Goals Fully test and exercise produced electronics, should improve understanding, quality and feedback Analogue readout of CPC2 Perform additional CPC2 measurements, build up CCD expertise Experiment with power provisions for the clock driver with real sensor and super-capacitors Oxford Test Setup Status Minimal configuration is functioning Sequencer based on BVM2 Agilent LV PS Oxford Bias PS controlled by BVM1 Agilent mixed-signal Oscilloscope used as ADC LabView code was mostly inspired by RAL examples Many thanks to Konstantin for help Measurements: X-ray signal Standard procedure : to enhance probability to have a Fe55 signal need to integrate long time ? need to operate at low temperature Our setup is running so far at room temperature ? accumulate substantial noise from leakage current Reduced integration time to minimum (3 msec) and used accumulation feature of the scope Measurements: X-ray signal RMS of Raw Noise : 2-4 mV Illuminated CPC2 with Fe55 X-ray source (5.9 keV) Signal : 15-20 mV ? useful calibration 18 mV expected based on expected amplification etc 1600 e from Fe55 ? ~100 e / mV Noise ~300 e (to compare to 50-100 e at RAL – ways to go!) Noise performance is poor as expected at room temperature and long integration time Had a setback using the ICS-554 PCI ADC Double PCI-PMC carrier does not fit in our PC ? ? ? Will exchange for a single carrier, here in a month Potentially ICS-554 will allow fast readout (faster than VME), it also has onboard large FPGA for pre-processing so further speed-up is possible (for ex setting a threshold and passing on to the PCI bus only events above the threshold) In the meantime tried to detect signal using scope trace readout to PC but this was too slow Concentrated on noise measurements Noise Analysis Examples on no