MOS-4-短沟道效应.ppt

短沟道效应 例题 2、高场效应——沟道方向电场 漏端峰值电场可达到 106 V/cm 2、高场效应——碰撞电离 2、高场效应——衬底电流 3、Drain Induced Barrier Lowering (DIBL) 4、穿通 穿通 5、寄生晶体管效应 例题：计算氧化层中辐射电离造成阈值电压的漂移量 短沟道器件的判据 LDD结构 LDD工艺 栅氧化层厚度 Rochester Institute of Technology,Microelectronic Engineering L=0.75 um Xox=300 ? D/S Xj = 0.25 μm P+ poly Nd well ~3E16 Vt = -0.15 Sub Vt Slope=130 mV/dec CMOS结构 The CMOS Inverter Advantages: low power consumption good noise immunity Vin=0 PMOSFET is on NMOSFET is off Vout=VDD Vin=VDD PMOSFET is off NMOSFET is on Vout=0 CMOS及其闩锁效应 Latch-up闩锁效应 The cause of latch-up is the action of the parasitic p-n-p-n diode, which consists of a lateral p-n-p and a vertical n-p-n bipolar transistors, in the well structure. 可控硅的电流增益等于两个晶体管的共发射极增益的乘积，一旦变成低阻态，将有很大的电流通过。称之为闩锁效应。不稳定因素，如瞬时电流、电离辐射在阱和衬底中引起的横向电流，双极晶体管的发射极基极正偏都可激活寄生的可控硅开关形成闩锁。 要求：寄生晶体管的增益小、寄生电阻小 The methods of avoiding latch-up: Reducing the current gains parasitic BJT A deeper well structure Using a heavily doped substrate With the trench isolation scheme 为降低SCE效应，栅氧化层要尽可能薄，但需要考虑可靠性。 最大电场取 Fowler-Nordheim (F-N)隧穿开启电场的 80%。即 5 MV/cm的80%，为 4 MV/cm 例如： 工作电压2.5V 最大电场4 MV/cm 所以氧化层厚度 Xox = 2.5 V/4MV/cm = 65? 栅的介电性能及失效 介质失效 7/22/94 Electron beam direct write on wafer, nwellprocess 5E12 dose, P+ Poly Gate PMOS, shallow BF2 D/Simplant, no Vt adjust implant * * EE130 Lecture 41, Slide * EE130 Lecture 41, Slide * 1、阈值电压漂移 栅控耗尽区 n+ n+ VG p depletion region Large L: S D Small L: D S S/D控耗尽区 S/D控耗尽区 rj n+ (p-Si) ?LD Junction Depletion Region xdD xj xj xdm For 5 μ, effect is negligible. But at 0.5 μ, VT0 reduced to 0.43 from 0.76 volts (ΔVT0=0.33V) Channel Length (μm) Threshold Voltage (V) 沟道变窄 QNC QNC xdm W Thin Gate Oxide Thick Field Oxide Substrate (p) Gate Drain Diffusion (n+) We consider an n-channel MOS process with the following parameters: substrate doping density NA=1016 cm-3, polysilicon gate doping density ND (gate) = 2 1020 cm-3, gate oxide tickness tox= 50 nm, oxide-interface fixed charge density Nox=4*1010cm-2 , source and