AT25F1024N-10SI-2.7;AT25F512N-10SI-2.7;中文规格书.Datasheet资料.pdfVIP

Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • 20 MHz Clock Rate • Byte Mode and 256-byte Page Mode for Program Operations • Sector Architecture: – Two Sectors with 32K Bytes Each (512K) – Four Sectors with 32K Bytes Each (1M) – 128 Pages per Sector • Product Identification Mode • Low-voltage Operation SPI Serial – 2.7 (VCC = 2.7V to 3.6V) • Sector Write Protection Memory • Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection • Self-timed Program Cycle (60 µs/Byte Typical) 512K (65,536 x 8) • Self-timed Sector Erase Cycle (1 second/Sector Typical) • Single Cycle Reprogramming (Erase and Program) for Status Register 1M (131,072 x 8) • High Reliability – Endurance: 10,000 Write Cycles Typical • Lead-free Devices Available AT25F512 • 8-lead JEDEC SOIC and 8-lead SAP Packages AT25F1024 Description The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash memory organized as 65,536/131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-volt- age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages. The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles