operating system《操作系统》ch08-main memory-57讲义教材.ppt

Chapter 8: Main Memory;8.1 Background;Base and Limit Registers;HW address protection with base and limit registers;Binding of Instructions and Data to Memory;Multistep Processing of a User Program ;Logical vs. Physical Address Space;Memory-Management Unit (MMU);Dynamic relocation using a relocation register;Dynamic Loading;Dynamic Linking;8.2 Swapping;Schematic View of Swapping;8.3 Contiguous Allocation;Contiguous Allocation (Cont.);Dynamic Storage-Allocation Problem;Fragmentation;8.4 Paging;Address Translation Scheme;Paging Hardware;Paging Model of Logical and Physical Memory;Paging Example;Free Frames;Implementation of Page Table;Associative Memory;Paging Hardware With TLB;Effective Access Time;Memory Protection;Valid (v) or Invalid (i) Bit In A Page Table;Shared Pages;Shared Pages Example;8.5 Structure of the Page Table;Hierarchical Page Tables;Two-Level Table Scheme;Two-Level Paging Example;Address-Translation Scheme;Three-level Paging Scheme;Hashed Page Tables;Hashed Page Table;Inverted Page Table;Inverted Page Table Architecture;8.6 Segmentation;User’s View of a Program;Logical View of Segmentation;Segmentation Architecture ;Segmentation Architecture (Cont.);Segmentation Hardware;Example of Segmentation;8.7 Example: The Intel Pentium;Logical to Physical Address Translation in Pentium;Intel Pentium Segmentation;Pentium Paging Architecture;Linear Address in Linux;Three-level Paging in Linux;End of Chapter 8