多层PCB信号完整性建模与边界元数值分析-机械设计及理论专业论文.docxVIP

多层PCB信号完整性建模与边界元数值分析-机械设计及理论专业论文.docx

  1. 1、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
  2. 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  3. 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
  4. 4、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
  5. 5、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们
  6. 6、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
  7. 7、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
多层PCB信号完整性建模与边界元数值分析-机械设计及理论专业论文

II II Signal Integrity Model of Multilayer PCB and Boundary Element Method Numerical Analysis Abstract Nowadays, under the trend of Electronic products are miniaturization、high speed and high density, which lead to the number of layers and vias are increasing in High-speed printed circuit board (PCB). Under the condition of high frequency, the parasitic effect is more complicated than the low frequency, at the same time the parasitic effect has become the important factors of affecting the signal transmission quality in the high speed PCB. Meanwhile, the high-speed signal through the interconnect lines will produce some signal integrity trouble, such as delay, reflection, crosstalk, attenuation and dispersion. Predicting the influence of via and modeling for vias have become very important component in the process of high-speed PCB design. In addition, these directly affect the success or failure of high speed digital system design. In this paper, the boundary element method was used to mode, simulate and analysis resonator structure,which is composed of power/ground plane. According to the analysis of the field distribution within the power/ground plane, the complex 3-d problems convert to 2-d problem. Study numerical method of the return path input impedance on power/ground plane, which containing some vias , shorting vias and shorting via ,which are located around the signal via. First of all, according the vias and interconnect structure on multilayer PCB to modeling equivalent circuit, using transmission line theory and PSPICE prediction crosstalk between different microstrip at the source side line. Second, using the boundary element numerical method to calculate the return path impedance and apply PSPICE (ADS) to simulating reflection coefficient and transmission coefficient. In the meantime, analyze the influence of parameters of via, the number of shorting via and the gap between signal via and shorting vias for signal transmission. At last , through the HF

您可能关注的文档

文档评论(0)

peili2018 + 关注
实名认证
文档贡献者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档