数字设计课件 第6章 组合逻辑设计实践2教学材料.ppt

Chapter 6 Combinational Logic Design Practices;2. Active levels for pins;;3. bubble-to-bubble logic design;6.3 Combinational PLDs;;;2. Programmable Array Logic Devices;3. Generic Array Logic Devices（GAL）;6.4 Decoder;1、bianry decoders;;（2）74×139 , dual 2-4 decoder;（3）74××138, 3-8 decoder;EN;2、realizing combinational circuits with decoder;;;3. Cascading binary decoders;Exp：a 4-16 decoder;;Exp：4-bit prime-number detector. Realizing it with 74×138 and some gates.;4、7-segment decoder;;;5、BCD decoder（二—十进制译码器）;5.5 Encoder;8-3 encoder;;2、Priority Encoder;;Logic expressions for priority encoder;3、