数字设计课件 第七章 时序逻辑设计原理2教学材料.ppt

Chapter 7sequential logic design principles;Some important concepts;7.1 Bistable Element;analysis with transfer characteristic;;7.2 Latches and Flip_Flops;1、S—R Latches;; (2) minimum pulse width;(3) symbol and characteristic equation; 2、S-R latch ;3、S-R latch with enable;4、D latch;timing diagram;5、Edge-Triggered D Flip-Flops;positive-edge-triggered D flip-flop;;Others;6、edge-triggered D flop-flop with enable;frequency divider with D f-fs;7、scan flip-flop;;8、master/slave S-R触发器;C;9. master/slave J-K flip-flop;JK flip-flop timing diagram;features;1s catching;0s catching;10、Edge-trigg