第8章-FFT-v1.0.pptVIP

Decimation-in-Time FFT Algorithm In the DFT computation scheme outlined, the DFT samples X[k] appear at the output in a sequential order while the input samples x[n] appear in a different order Decimation-in-Time FFT Algorithm Thus, a sequentially ordered input x[n] must be reordered appropriately before the fast algorithm described by this structure can be implemented To understand the input reordering scheme represent the arguments of input samples x[n] and their sequentially ordered new representations in binary forms Decimation-in-Time FFT Algorithm The relations between the arguments m and n are as follows: m: 000 001 010 011 100 101 110 111 n: 000 100 010 110 001 101 011 111 Thus, if ( b2b1b0 ) represents the index n of x[n], then the sample x[b2b1b0 ] appears at the location m= b0b1b2 before the DFT computation is started, which is in bit-reversed order Indirect Addressing in DSP Bit-Reversed Addressing Bit-reversed addressing enhances execution speed and program memory for FFT algorithms that use a variety of radixes. An auxiliary register points to the physical location of a data value. When you add AR0 to the auxiliary register using bit-reversed addressing, the address is generated in a bit-reversed fashion, with the carry bit propagating from left to right, instead of the normal right to left. carry bit from right to left and from left to right 1 0 0 + 1 0 0 ———— 1 0 0 0 1 0 0 + 1 0 0 ———— 0 1 0 Bit-Reversed Addressing AR0 = 100 AR1 = 000 Addressing by AR1, then add AR0 to the AR1 with the carry bit propagating from left to right original original bit-reversed bit-reversed order address address order 0 000 000 0 1 001 100 4 2 010 010