基于FPGA的改进ASB纠错算法设计与实现.docVIP

基于FPGA的改进ADS-B纠错算法设计与 实现 胡铁乔刘丹阳李阳波 宣 基于S模式数据链技术的广播式自动和关监视(ADS-B)系统，凭借其建设成本 低及其精度高的优点而广泛用于空中交通管制等领域。然而，ADS-B系统的广播 性和信号非加密特点，在高A/C应答异步干扰(FRUTT)交叠的情况下，使得信 号在接收端被接收时极易产生误码。针对这一问题，结合FPGA的并行运算特性 与资源配置情况，在循环冗余编码(CRC)校验和置信度判定的基础上，提出了 一种基于FPGA的改进ADS-B纠错算法。给出了该改进算法的设计方案，并通过 FPGA平台进行了大量实采信号的测试验证。经多次测试的结果表明：在不影响纠 错性能的条件下，该改进算法可节省硬件开销，提升信号处理速度，保证了信 号传输的可靠性。 关键词： ADS-B系统;CRC校验;比特置信度;纠错;FPGA; 胡铁乔(1970一)，男，河南洛阳人，副教授，工学硕士，研宄方向 为基于FPGA、DSP高速处理平台的阵列信号处理系统. 2016-12-22 基金：W家重点研发计划(2016YEB0502402) Design and implementation of improved correction algorithm for ADS-B based on FPGA HU Tieqiao LIU Danyang LI Yansbo Intelligent Signal and Image Processing Key Lab of Tianjin, CAUC; Abstract： ADS-B (automatic dependent surveillance broadcast) system is based on Mode S data link, which is widely used in the field of air traffic management owing to its low cost and high precision. However, ADS-B is vulnerable to interference. The very severe overlapping Mode A/C False FRUIT (replies unsynchronized to interrogator transmission) environment leads to bit errors of ADS-B signal. In order to solve this problem, an improved signal correction method is presented combining with serial operation characteristics and resource allocation of FPGA, CRC (cyclic redundancy check) and bit confidence for 八DS-B signal. This method is designed and tested by FPGA platform. ADS-B signal test results of FPGA platform show that this improved method needs less hardware consumption and can improve signal processing speed without affecting the performance of error correction, ensuring the transmission reliability of ADS-B signal and making correction rate reaches 100%. Keyword： ADS-B System; CRC checkout; bit confidence; correction; FPGA; Received： 2016-12-22 广播式自动相关监视(ADS-B)是一种基于卫星导航系统和空-空、地-空、地- 地数据链通信的航空器运行监视技术，属于国际民用航空组织(TCAO, international civil aviation organization)定义的新航行系统(CNS/ATM, communications, navigation, surveillance/air traffic management)范畴。 机载设备通过周期性广播ADS-B信号，实时地、自发地播报飞机的高度、经纬度、 速度、呼号等精准信息。ADS-B是一种可弥补传统