3_8译码器的VHDL设计.docVIP

WORD格式可编辑 专业技术 资料分享 3-8译码器的VHDL设计 1.实体框图 2.程序设计 正确的程序 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODER38A IS PORT(A2,A1,A0,S1,S2,S3:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY DECODER38A; ARCHITECTURE ONE OF DECODER38A IS SIGNAL S: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN S=A2A1A0S1S2S3; WITH S SELECT YWHEN 000100, WHEN 001100, WHEN 010100, WHEN 011100, WHEN 100100, WHEN 101100, WHEN 110100, WHE