FPGA可配置端口电路的设计-微电子学固体电子学专业毕业论文.docxVIP

FPGA可配置端口电路的设计关键词：现场可编程门阵列端口电路边界扫描电路Cadence仿真 FPGA可配置端口电路的设计 关键词：现场可编程门阵列端口电路边界扫描电路Cadence仿真 IIIAbstract III Abstract Port circuits can be configured FPGA chip and the external circuit connecting key hub，it has many functions：chip-to·chip data transfer in(including the acquisition ofthe input signal and output signal output)，the voltage conversion of the external Chip drive, completion ofthe test functions，as well as chip-to—chip circuit protection． In this paper,using a top·down and bottom of the design method,based 011 port circuit can be configured to achieve the functional and working principle，the use of Cadence Design software，the combination of CRC，the 0．5∥m process，designed a performance、timing、power on the whole inferior xilinx4006e port circuit．On the following main aspects： 1．Port circuit signal based on the collection and output register,the paper port circuit design can be configured to set a singe-or dual—edge along the trigger,and completed Vcdlog_XL and Hspice functional and timing simulation,and set-up time is less than 5 11s and maintain 0 ns time around．And xilinx4006e compared to satisfy the design requirements． 2．TAP Controller based on the working principle and its 1 6 state machine conversion control of the state machine 1 6 completed the conversion of the class described and the achievement of capture，shiR，output，update and major functional simulation． 3．Based on the boundary-scan circuit Trigger Cascade framework of this，a boundary-scan design of the circuit,and Bse Verilo盥and Hspice，and conduct functional and timing simulation．To test the chip circuit design requirements． 4．To port circuit speaking，sometimes，the CLB will need to output data to achieve XOR、NOR、 And and OR．So the functions of this paper using quadratic function of the output circuit structure to achieve the above functions，and use Hspice and Verilog■L to the functional and timing simulation．Meet the design requirements． 5．To 0．5∥m process，the input voltage is usually 5 V and