基于pld的时间数字转换电路设计-电路与系统专业论文.docxVIP

基于PLD的时间数字转换电路设计 基于PLD的时间数字转换电路设计 郑州大学硕士研究生论文 This paler is study∞TDC(Time to Dig瞄Conversion)technology which serves for digital ADC(Analog to digit converter)design．Digital ADCⅢbe realized indifect矿棚．Firstly,ATC (AnalogtoTimeConvemon)isdonewhichtransfers signalsformanalogtotime．And secondly, TDC ffansf日8 the analog time signal into digital signal．This aim limits the way ofour design．It m啪sthatwe啪maymkell∞ofpresentwaysusedinotherfieldsbutwe shouldlookafterour goals first Our goal5 have some requirements main ofwhich端the circuit designed must be fully digital, analogdevice8likecommonlyusedVCOcouldnotbemed：eitherrealizationonASICandPLDi曩 requL,ed,this results ahighdemandon synthesizingandthecircuit$mtleonthechip．Ofcom“seatthe omedn‰the samplingrate andtheresolutionmustbe satisfied． so妣theapplicationsofTDC雠fidlydevelopedinfieldslikenwlwphysi璐【删，but still few designs w∽reported those serving for digital ADC．Wantanabe(inl993)reported design using structure called‘Ring Delay Gate Line’which was 13-bit digital TDC and manufactured 1．1mm 2chipin0．StunCMOSline．Thechip reacheda resohtionof0．5ns．Laterin2003． Wantanabe realized an all digital ADC design based his TDC designl”．An ASIC chip was manufacaa司on 0．45 chip in 0．8um CMOS line． Unfortunately,theATCwayusedbyWantanabeinpape一”nscsdieprinciplewhichpointsout thatthedelaytimeforaCMOSgateisproportionaltothevoltageappliedonit．Itisnotpossiblefor PLD realization bused the principle．We all know that ASIC realization has many disadvantages such high design effort and ooBL high manufacturing risk,and hard design eto．As the developmeat ofhigh resolution digital TDC，the PLD realization ofdigit TDC bccolnes possible． This paper focuses the PLD realization ofdigit TDC．The realization ofWantanabe‘s way for TDC design is introduced．And lots ofproblems have to be solved to realize the design．Test results given in this paper based EPM7128SLC84-15 CPLD chip belonging to MAX7000S seriesIl7l and the resolution is 4．26ns wjnl nonlinearity