译码器的设计.doc

word文档 可自由复制编辑 译码器的设计 architecture dec_behave of e1 is Signa lsel : std_logic_vector( 0 to 3) ; begin sel(0) = en ; sel(1) = a(0) ; sel(2) = a(1) ; sel(3) = a(2) ; with sel select y = when 1000, when