基于fpga的mjpeg编码器的研究及实现-计算机应用技术专业论文.docxVIP

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基于fpga的mjpeg编码器的研究及实现-计算机应用技术专业论文.docx

基于fpga的mjpeg编码器的研究及实现-计算机应用技术专业论文

摘 摘 要 在视频传输系统中,最大障碍是视频数据的大数据量传输。故压缩就显得尤 为必要。MJPEG是以25帧每秒传输的JPEG图像。本文根据JPEG基本压缩模式, 通过前端图像采集芯片输出标准的4:2:2格式的图像流,在XlLINX公司的 SPARTAN IIE芯片下压缩,获得了良好效果,压缩比达到lO:1。中间的各个环 节同MATLAB下同等压缩相比,除了精度上有点差别外,基本一致。同专用芯片 相比,比专用芯片灵活得多,FPGA内部全部是可编程,烧写不同的程序便可实 现不同的压缩。同DSP相比,压缩时间极大的提高,同周霖的“基于DSP技术 的静态图像压缩编码”一文中编码所需的时间进行比较(DCT变换消耗4224个 指令,量化Z排序耗960指令,huffman编码至少耗1400指令),假设令其采用 6000系列DSP,指令周期为6ns,运算速度为1336MIPS。压缩一个8*8DCT块。采 用高档的DSP,消耗39us,而采用27M的FPGA只需6us,若采用FPGA内部自带的 DLL将时钟倍频到54M,则只需要3us.本设计同传统的压缩实现方式相比,在速 度和灵活性上有了极大的提高。 关键词:FPGA;JPEG;压缩;DCT 东北电力大学顾士学位论文Abstract 东北电力大学顾士学位论文 Abstract In the video transmission system,the biggest barrier is the great data quantity. Therefore video compression appears especially essential.MJPEG is a standard which specifies that the system should transmit 25 flames JPEG picture per second. According to the JPEG basic compact model,this article discusses the compression that the standard 4:2:2 forms picture stream which generated by picture gathering chip,is compressed in XILINX Corporation’S SPARTAN IIE,obtained good effect. the compression ratio achieve 10:1.Each step.simulated in modelsim,compared witll MATLAB,besides the precision in the difference,the result is consistent.The realization of the compression articled in this article. compares with in special-purpose chip,it is much more fexible.The FPGA interior is completely programmable,download different procedure will realize different compression. Compared witll DSP,the time of compression reduce much.Compared with the time consume claimed in the article which written by zhoulin”based on the DSP technology static image compression encode’’(the DCT transformation consume 4,224 instructions,the quantification and Z scan consul/les 960 instructions,the Huffman encode at least consumes 1,400 instructions),supposed it use 6,000 series DSP,the instruction cycle is 6ns,the operating speed is 1336MIPS,Compressing a 8+8DCT block,uses DSP,consumes 39us,but ases 27M FPGA only need 6us,if uses DLL by which the FPGA

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