基于fpga的视频采集与预处理系统的研究与设计-集成电路工程专业论文.docxVIP

基于fpga的视频采集与预处理系统的研究与设计-集成电路工程专业论文.docx

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基于fpga的视频采集与预处理系统的研究与设计-集成电路工程专业论文

万方数据 万方数据 Abstract With the development of integrated circuit technology, image processing has been widely used in many fields of applications. The traditional image processing system is usually implemented with ASIC(Application Specific Integrated Circuit) and DSP(Digital Signal Processors), and has been limited in some certain applications because of cost and speed. FPGA has abundant logic resources and can be configured flexibly, with the advantages of parallel processing and pipelining in hardware. All these accelerate the speed of image processing, and let FPGA be widely used in the field of image processing. This paper introduces the present status of video acquisition and image processing system, and expounds the principle of programmable logic devices. On this basis, a video capture and image pre-processing system is designed and realized. In this system, the Altera’s FPGA chip is used as the main processing chip and OV7670 works as the image sensor chip cooperated with SDRAM memory, which realizes video information collection, storage, display and transmission. The system is divided into several modules according to function as follows: the reset module, video capture module, color space conversion module, video storage module and VGA display module. All these modules are realized in the FPGA chip with Verilog HDL hardware language respectively. In terms of image pre-processing, a fast median filtering algorithm is implemented on FPGA, which effectively eliminates the noise in image acquisition and transmission process while achieving a better filter effect. The design not only make full use of the advantage of parallel processing and abundant logic resources of the FPGA, but also apply ping-pong operation and pipelining technology to accelerate image processing speed. At the same time, as the FPGA is re-configurable and the Verilog HDL language is portable, the system is easy to upgrade and maintain. Finally, the system is validated and debugging, and the

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