dsp指令集模拟器的设计与实现计算机应用技术专业论文.docxVIP

AbstractInstruction Abstract Instruction Set Simulator(ISS)iS a system used in the structure of the implementation of another kind of computer architecture computer software．It targets machine simulation software instruction set architecture for a11 the functions of instruction execution，so as to achieve the target machine and execute the same functions and results． ThiS paper introduces the technology of instruction set simulator used to Simulate the function of the internal DSP and DSP instructions to test whether the design iS right．The technology by USing C++language on the Instruction Set Architecture(ISA)instruction set simulator model ing completed the design，engineering and the later Verification proved itS validity． The workload of verification increases exponentially as the continuous improvement of IC design automation and chip scale．Usually the RTL code in system increases one more time，while four times or more tasks are needed to verify it．The disadvantage of traditional verification method has been not adapt for nowadays large scale DSP processor．How to cut verification cost and increase verification efficiency has become a challenge．ThiS thesiS presents a verification method which iS used to verify each lonelY module before system integrating．In the top level，a SystemC model iS created to verify the entire DSP core．Testcases are written to stimulate both ISA model and HDL model，and bugs can be found quickly thanks to the comparison of two results．The verification method，used in a DSP processor named DSP(developed by CETC 38th institude)，increase design automation level and save the verificat ion time．The verificat ion platform can be used as a standard environment for DSP verification because of its good reusability． Key Words：DSP，Instruction set，simulator，verification platform 插图目录图1-1芯片设计流程 插图目录 图1-1芯片设计流程 6 图1-2 IC前端设计流程 9 图2-1二进制的测试结果文件 ．25 图3-1模拟器的处理过程 ．30 图3-2 DSP的4级流水线 30 图3-3 DSP指令集模拟器流程图 ．3 1 图4-1传统的验证结构示意图 ．35 图4-2引入删的验证结构示意图 35 图4-3 DSP前端设计