基于X87指令集的浮点加法单元的设计与验证-电路与系统专业论文.docxVIP

基于X87指令集的浮点加法单元的设计与验证-电路与系统专业论文.docx

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万方数据 万方数据 Abst Abstract Title: Design And Verification Of Floating-point Adder Unit Based on X87 Instruction Set Major: Circuit and System Name: Ming Zhang Signature: Supervisor: Prof. Ningmei Yu Signature: Associate Prof. Liping Zheng Signature: Abstract X87 instruction set is the most widely floating-point instruction set for CISC architecture microprocessor, Floating-point addition instruction is one of the most frequent use of floating-point instructions, so efficient design of the floating-point adder unit can improve the ability of the microprocessor, meanwhile promote processor performance effectively. In the thesis, the design is based on CISC microprocessor design projects. the floating-point adder unit is compatible with Intel X87 instruction set, using TSMC 65nm technology library, whose the operating frequency up to 900MHz. The author is charge of the design and verification of float add instructions, data transfer instructions, comparison instructions. The main contents are listed as followed: 1. Analyzing the Intel X87 instruction set in deep, studying the floating-point data register and X87 FPU execution environment in detail. 2. A floating-point addition operation unit for Intel X87 instruction set is designed and implemented. Design a multi-channel floating point adder scheme, which elaborated implementation process of floating-point addition instruction, structure and each module design of the floating-point addition operation unit. FPU design, including floating point adder unit is completed by using Verilog HDL, and the combined result of the overall design meets the requirements of the processor. 3. In addition, system verilog test platform based on VMM verification methodology is developed, which includes reference model in C language. The design under test is detected by a constrained large-scale random test and direction test, then analyzing the function coverage report , the function coverage can satisfy the verification requirement. The t

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