基于多DSP的航迹规划系统硬件平台设计与实现-模式识别与智能系统专业论文.docxVIP

华 华 中 科 技 大 学 硕 士 学 位 论 文 II II Abstract As the core of mission planning system, path planning plays an important role in improving the penetration ability and precision strikes of accurate-attacking weapons. How to improve the planning speed is one of the important topic about path planning. There are tow means to improve the speed of path planning. One is to deal with fast algorithm to increase the efficiency of the algorithm, while another is to use a hardware platform performance of path planning system. This thesis focuses on the second strategy, and a Multi-DSP(3-pieces of TMS320C6455) path planning platform is designed. The main work of this thesis is as follows: The main chip is selected based on the data-intensive feature of path planning system. Then Multi-DSP interconnected scheme is discussed and the hardware platform scheme is designed. The hardware system contains following modules. The fist one, external interface module includes PCI bus and Gigabit Ethernet. The second one, storage expansion module includes DDR2 SDRAM, Flash and I2C EEPROM. The third one, interconnection module includes interconnection by EMIF and McBSP. The other modules such as FPGA core circuit, clock, power, monitor and reset circuit, JTAG interface .etc were also designed. The PCB of hardware system is completed under the guidance of high-speed circuit design theory. A new multi-DSP parallel interconnected structure based on bus arbitration is presented, which has the features of simple structure, flexible data transfer and multiple DSPs in equal status. Within FPGA bus arbitration and communication protocol are realized. The results of experiment showed that data transferred among DSPs are stable with high-bandwidth. Finally, the application of hardware platform in route segment planning systems is introduced and the experimental results and analysis are given. Key words: Path Planning, DSP, High-Speed Circuit Design, Interconnection, Route Segments. 独创性声明 本人声明所呈交的学位论文是我个