基于多核多线程网络处理器的高性能ipv6路由查找算法研究-计算机软件与理论专业论文.docxVIP

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基于多核多线程网络处理器的高性能ipv6路由查找算法研究-计算机软件与理论专业论文.docx

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中国科学技术大学学位硕：仁论文Abstract 中国科学技术大学学位硕：仁论文 Abstract IP forwarding has become one of main performance bottlenecks in Internet backbone routers，as it requires performing longest-prefix match(LPM)at 1 0Gbps speed or higher．IPv6 forwarding further exacerbates this situation because its search space is quadrupled from 32 bits to 1 28 bits． This paper proposes a high-performance IPv6 forwarding algorithm with incremental prefix update support，TrieC，and its efficient implementation on Intel mulit-core and multithreaded IXP2800 network processorⅢPU)． Based on the fixed five-level TrieC tree built with Modified Compact Prefix Expansion(MCPE)technique，TrieC algorithm not only achieves high-speed lookup by reducing memory accesses but also eliminates the redundant next·hop information caused by Traditional Prefix Expasion(TPE)． TrieC is experimented with an architecture—aware design principle tO guarantee the high performance of the resulting algorithm．According to the statistics of IPv4 prefix distribution，lPv6 address allocation scheme and existing IPv6 routing tables， this paper simulates TrieC on IXP2800 NPU with three group IPv6 routing tables with different prefix distribution，and three tables of different sizes 200K，300K and 400K in each group．Simulation shows that TrieC can support OC·192 line rate on Intel IXP2800 Besides，its almost linear speedup shows TrieC can achieve higher lookup speed． Programming the multi-core and multithreaded NPU is daunting task This paper studies the interaction between the parallel algorithm design and the architecture mapping to facilitate efficient algorithm implementation．We investigate the main software design issues that have dramatic performance impacts on any NPU based implementation：memory space reduction，instrliction selection，data allocation， task partitioning，latency hiding，and thread synchronization．Based on the detailed performance analysis of the TrieC algorithm，this paper also provides guidance on developing high-performance n