21 Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging外文电子书籍.pdfVIP

Chapter 21 Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging Lunyu Ma, Suresh K. Sitaraman(*ü ), Qi Zhu, Kevin Klein, and David Fork 21.1 Introduction Power and latency are fast becoming major bottlenecks in the design of high perform- ance microprocessors and computers. Power relates to both consumption and dissipa- tion, and therefore, effective power distribution design and thermal management solutions are required. Latency is caused by the global interconnects on the integrated circuit (IC) that span at least half a chip edge due to the resistance–capacitance (RC) and transmission line delay [1] . Limits to chip power dissipation and power density and limits on hyper-pipelining in microprocessors threaten to impede the exponential growth in microprocessor performance. In contrast, multicore processors can continue to provide a historical performance growth on most consumer and business applica- tions provided that the power efficiency of the cores stays within reasonable power budgets. To sustain the dramatic performance growth, a rapid increase in the number of cores per die and a corresponding growth in off-chip bandwidth are required [2] . Thus, it is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) (Table 21.1) that by the year 2018, with the IC node size shrinking to 22 nm by 2016 and 14 nm by 2020, the chip-to- substrate area-array input–output interconnects will require a pitch of 70 µm [3] . Furthermore, to reduce the RC and transmission line delay, low-K dielectric/Cu and