40nm高速嵌入式SRAM+IP设计.pdfVIP

Abstract Abstract SRAM play an important role in modern VLSI systems. Cache, which is formed by SRAM, is a bridge between CPU and main memory. With the shrinking of minimum feature size of MOSFET in standard CMOS process, process variation has a deeper impact on electronic performance of MOSFET. And it result with higher requirement of nano-scale VLSI chip design. For the purpose of meeting demands of high speed, high stability on-chip embedded SRAM in 40nm CMOS process, in this paper, an optimal 1024 ×32Bit SRAM with less access time and higher stability is designed under SMIC 40nm logic process. The cell layout area is 1.31×0.62µm2 . The chip simulation with RC delay model result shows that cycle time is less than 1ns under worst PVT case. And it also shows that the chip frequency is more than 1.5GHz under typical case. Firstly, with the deep research of SRAM 6T cell theory, facing the limit of advanced semiconductor technology, a large 6T cell is designed by systematic simulation to meet the high requirement of speed and stability. Secondly, for peripheral circuit, a high speed, less area consumption sense amplifier is designed with comprehensive simulation on the different data pattern in the column cells. Its offset voltage is reduced by increasing transition of SAEN. In the design of replica BL, reasonable quantity of discharge cells is chosen to reduce the variation of delay time. Finally, a new layout strategy with the avoidance of process impact is proposed on the base of layout floor-plan. And the memory cell layout is completed. Keywords: SRAM High Speed 6T Stability Sense Amplifier 目录