0.35μm40V+LDMOS器件ESD性能分析与优化.pdfVIP

ABSTRACT ABSTRACT In the semiconductor industry, with the improvement of integrated circuit’s integration and the reduction of device feature size, the potential damage induced by electrostatic discharge (ESD) to the IC chip has become more and more serious. With different process, the influence of various parameters to the device is different. What’s more, with different device structure, the influence of various parameters to the device also exists difference. So, it’s very important to study the effect of various parameters to the ESD protection devices under specific process. In this paper, we have studied the ESD characteristics of a GG-NLDMOS (Gate Grounded n-type lateral diffused MOS) device under 0.35 μm 40V BCD process. Firstly this paper introduces design mechanism and working principle of basic ESD protection devices and the ESD test models. Then this paper has studied TLP (Transmission Line Pulse) test results of the original GG-NLDMOS and found that the original GG-NLDMOS device exists serious non-uniformly turn on characteristic. And then the working characteristics of the original GG-NLDMOS device under ESD stress have been studied by TSUPREM4 and MEDICI simulation software. Then, the effects of various parameters to the GG-NLDMOS are studied. They include channel length 、 LOCOS length of Drain 、substrate resistance and plate length in the active region. The substrate resistance is changed by changing the distance between substrate contact and N+ region of the source and reducing the area of the substrate contact. Th