ADCLK854BCPZ;ADCLK854PCBZ;中文规格书,Datasheet资料.pdfVIP

1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs ADCLK854 Selectable LVDS/CMOS outputs LVDS/ V /2 CMOS OUT0 (OUT0A) Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs VREF S 12 mW per channel (100 MHz operation) OUT0 (OUT0B) 54 fs rms integrated jitter (12 kHz to 20 MHz) CLK0 OUT1 (OUT1A) 100 fs rms additive broadband jitter CLK0 OUT1 (OUT1B) 2.0 ns propagation delay (LVDS) CLK1 OUT2 (OUT2A)