CD4075 CMOS 3输入端三或门.pdfVIP

CD4071BMS, CD4072BMS CD4075BMS December 1992 CMOS OR Gate Features Pinout • High-Voltage Types (20V Rating) CD4071BMS TOP VIEW • CD4071BMS Quad 2-Input OR Gate • CD4072BMS Dual 4-Input OR Gate A 1 14 VDD • CD4075BMS Triple 3-Input OR Gate B 2 13 H • Medium Speed Operation: J = A + B 3 12 G - tPHL, tPLH = 60ns (typ) at 10V K = C + C 4 11 M = G + H • 100% Tested for Quiescent Current at 20V C 5 10 L = E + F • Maximum Input Current of 1µA at 18V Over Full Pack- o D 6 9 F age Temperature Range; 100nA at 18V and +25 C VSS 7 8 E • Standardized Symmetrical Output Characteristics • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V