基于数字通信系统的可编程逻辑器件宏单元的一种建立方法-电路与系统专业论文.docxVIP

摘 摘 要 随着可编程逻辑器件的发展，FPGA的应用已经越来越广泛，且用可 编程逻辑器件代替传统的普通集成电路已成为一种发展的趋势。可编程逻 辑器件FPGA以其高集成度、高速度、开发周期短、稳定性好而受到了人 们的青睐，并得到了广泛的应用。 本文的主要工作是提出一种基于数字通信系统的可编程逻辑器件宏 单元的建立方法，使得它在数字通信系统的应用设计中具有更高的性能和 资源利用率。 本文首先分析和比较了目前各种可编程逻辑器件的结构，并结合数字 通信系统的特点，提出了一种宏单元结构。该宏单元结构采用了LUT (Look Up Table)结构，并具有快速进位逻辑和级联链设计、实现快速 乘法运算的“与”门设计、多端日的输出设计、多寄存器设计等，这些措 施都极大地改善了数据的处理速度和硬件资源的合理利用。然后，本文又 利用～些数字通信系统应用中的一些常用电路对所设计的宏单元进行了 评估，结果表明所设计的宏单元在性能、资源利用率上都达到了设计要求。 关键词：宏单元；LuT；进位逻辑；数字通信；性能；资源利用率 ABSTRACTIn ABSTRACT In recent years the use of programmable devices has increased in many areas because they have shorter design and production-cycle times and justify lower-volume production than application—specific integrated circuits(ASICs)． Among也e many allernatives in programmable devices，Field Programmable Gate Arrays(FPGAs)have shown significant Success in recent years because they can provide all the benefits ofprogrammable devices while exceeding the performance ofASICs． This dissertation focuses on devising a sort of programmable logic devices macro cell structure basing on digital communication systems．It owns high performance and high use ratio in digital communication systems application． In this paper,we firstly analyse and compare commercial programmable logic devices diveisified structure．Then we devise son of programmable logic devices macro cell structure combining with digital communication systems’characteristic．This macro cell adopts LUT(100kup table)structure，and fast carry logic and cascade chain design，“and” gate design for implementing fast multiply operation，many out ports design，many registers design etc．These measures improve on data processing rate and hard resource reasonable use ratio．Whereafter we evaluate this macro cell on some di百tal communication systems’ basic modules．The results indicate the macro cell designed have all reached the designing requirement on performance，resoBlce utilization ratio． Key words： macro cell；LUT=carry logic；digital communication；performance resource util