华为_VHDL设计风格和实现.pptVIP

Example; If we need to determine if a XC4000XL-1 will be able to manage a clock frequency of 66Mhz and contain three levels of logic, then we can perform the above calculation. We have estimated routing delays using the 50% rule. For more accurate results, we must place and route the design. A CLB delay is from any FG input to X,Y possibly through H as below; F G H CLB delay ( Tiho ) CLB delay ( Tilo ) Similar calculation to previous. The XL devices have eight global buffers. Buffers not used for clocking should be considered and used for signals with a high fan-out, or nets requiring a l