第7章章节可编程逻辑器件.pptVIP

attribute LOC of p: signal is p7; attribute LOC of q: signal is p8; attribute LOC of h: signal is p9; attribute LOC of i: signal is p11; attribute LOC of j: signal is p12; attribute LOC of u: signal is p18; attribute LOC of v: signal is p17; attribute LOC of w: signal is p16; attribute LOC of x0: signal is p15; attribute LOC of y0: signal is p14; attribute LOC of z0: signal is p13; END example1; ARCHITECTURE example1_architecture OF example1 IS BEGIN u=NOT a; v=b AND c; w=d OR e; x0=NOT(m OR n); y0=p XOR q; z0=NOT(h AND i AND j); END example1_architecture; 用GAL实现组合及时序混合电路 ⒈设计说明及构思 组合和时序混合的逻辑电路如图7-31所示。 建立用户源文件 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY example2 IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC; S : IN STD_LOGIC; B : IN STD_LOGIC; D : IN STD_LOGIC; I : IN STD_LOGIC; E : IN STD_LOGIC; OE : IN STD_LOGIC; X1 : OUT STD_LOGIC; QD : OUT STD_LOGIC; QA : OUT STD_LOGIC; QB : OUT STD_LOGIC; Y : OUT STD_LOGIC); 建立用户源文件 attribute LOC :string; attribute LOC of CLK: signal is p1; attribute LOC of A: signal is p2; attribute LOC of S: signal is p3; attribute LOC of B: signal is p4; attribute LOC of D: signal is p5; attribute LOC of I: signal is p8; attribute LOC of E: signal is p9; attribute LOC of OE: signal is p11; attribute LOC of X1: signal is p18; attribute LOC of QD: signal is p16; attribute LOC of QA: signal is p15; attribute LOC of QB: signal is p14; attribute LOC of Y: signal is p13; END example2; 建立用户源文件 ARCHITECTURE behavioral OF example2 IS SIGNAL QD_TEMP,QA_TEMP,QB_TEMP:STD_LOGIC:=0; BEGIN PROCESS(A,B,S) BEGIN X1=(A AND S) OR (B AND (NOT S)); END PROCESS; PROCESS (I,E) BEGIN IF(e=1) THEN Y=NOT I; ELSE Y=Z; END IF; END PROCESS; 建立用户源文件 PROCESS (CLK) BEGIN IF(CLKEVENT AND CLK=1) THEN QD_TEMP=D; END IF; END PROCESS; PROCESS (CLK) BEGIN IF(CLKEVENT AND CLK=1) THEN QA_TEMP=NOT