Israel KorenSpring 2008课件.pptVIP

Copyright 2008 Koren ECE666/Koren Part.6a.* Israel Koren Spring 2008 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical Computer EngineeringDigital Computer Arithmetic ECE 666 Part 6a High-Speed Multiplication - I Speeding Up Multiplication Multiplication involves 2 basic operations - generation of partial products + their accumulation 2 ways to speed up - reducing number of partial products and/or accelerating accumulation 3 types of high-speed multipliers: Sequential multiplier - generates partial products sequentially and adds each newly generated product to previously accumulated partial product Parallel multiplier - generates partial products in parallel, accumulates using a fast multi-operand adder Array multiplier - array of identical cells generating new partial products; accumulating them simultaneously No separate circuits for generation and accumulation Reduced execution time but increased hardware complexity Reducing Number of Partial Products Examining 2 or more bits of multiplier at a time Requires generating A (multiplicand), 2A, 3A Reduces number of partial products to n/2 - each step more complex Several algorithm which do not increase complexity proposed - one is Booths algorithm Fewer partial products generated for groups of consecutive 0’s and 1’s Booth’s Algorithm Group of consecutive 0’s in multiplier - no new partial product - only shift partial product right one bit position for every 0 Group of m consecutive 1s in multiplier - less than m partial products generated ...01…110... = ...10...000... - ...00...010... Using SD (signed-digit) notation =...100...010... Example: ...011110... = ...100000... - ...000010... = ...100010... (decimal notation: 15=16-1) Instead of generating all m partial products - only 2 partial products generated First partial product added - second subtracted - number of single-bit shift-right operations still m - - Booth’s Algorithm - Rules Recoding multiplier xn-1 xn- 2...x1 x0 in SD c