河南师范大学计算机组成与结构课件第三章 计算机功能和互联概要.pptVIP

Chap.3 A Top-Level View and Interconnection An instruction cycle consists of an instruction fetch(取), followed by zero or more operand fetches,followed by zero or more operand (操作数) stores, followed by an interrupt(中断) check(if interrupts are enabled). The major computer system components (processor,main memory,I/O modules)need to be interconnected in order to exchange data and control signals. The most popular means of interconnection is the use of a shared system bus consisting of multiple lines. In contemporary systems,there typically is a hierarchy(层次) of buses to improve performance. Key