西安电子科技大学通信工程学院信息论与编码理论（研究型）课件第4章 组合逻辑电路.pptVIP

Ch2. 作业 (P37) 4.8 Solving Larger Problem 4.8.1 and 4.8.2 sections will be read by student-self . 4.8.2 An error coding and decoding system(P268) A block diagram of the system is shown below. Solution process: Section 1 : design coder Step1: List the truth table of coder Step2: realize the logic circuit with ROM Section 2 : design decoder When a 5-bit word is received, there are three possibilities. First, no error: If abcde=xyzvw then pqr=xyz, flag f=1,g=1 Second, a single error matches only one transmitted word: If abcde=00111--xyzvw=00011 then pqr=xyz, flag f=0, g=1 Finally, a single error could come from two or more different transmitted words : If abcde=00010 --xyzvw=00011 or 01010 then p=x, q=0 or 1, r=z , flag f=0, g=0 Step1: List the truth table of coder .Step2: realize the logic circuit with ROM a b c d e p q r f g 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 x 0 0 0 0 0 0 0 1 0 0 x 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 x 1 0 0 0 0 1 1 0 x 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 x 1 0 0 0 We are designing two systems that are to be used in conjunction with an error detection and correction scheme . We have 3 bits of information to be coded and transmitted. We will code these into 5-bit words, where the first 3 bits are just the information. The fourth bit is chosen such that there is an odd number of ones in bits 1,3,and 4. The fifth bit is chosen such that there is an odd number of ones in bits 2,3, and 5 . Transmission media coder Decoder/ corrector z y x v w x y z a b c d e p q r f g Note: When the 5-bit words are transmitted, an error may occur during that transmission. Here, we will design the system under the assumption that at most one error occurs in a 5-bit word. An error results in one of the 1’s changing to a 0, or one of the 0’s changing to a 1. The description of coder The fourth bit is chosen such that there is an odd number of ones in bits 1,3,and 4.