A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning 4 MHz的CMOS连续时间滤波器的自动调谐芯片.pdfVIP

750 IFEE JOURNAL O t SOLID-STATE CIRCUITS, VOI 23, NO 3, JIJNE 1988 A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning FRANCOIS KRUMMENACHER AND NORBERT JOEHL Abstruct -This paper presents a third-order elliptic low-pass continu- t h s integrator configuration potentially achieves the best ous-time filter with a 4-MHz cutoff frequency, integrated in a 3-pm p-well hgh-frequency performance because it makes use of a CMOS process. The design procedure is based on the direct simulation of single source-coupled differential pair to implement the a doubly terminated LC ladder filter by means of capacitors and fully balanced, current-controlled transconductance amplifiers with extended voltage-to-current converter function (as opposed to con- linear range. The on-chip automatic tuning circuit uses a phase-locked loop figurations with multistage operational amplifiers which implemented with an 8.5-MHz controlled oscillator that matches a specific suffer from large amounts of excess phase at h g h two-integrator loop of the filter. The complete circuit features 70-dB frequency, causing unacceptable errors in the filter re- dynamic range (THD -50 dB) and consumes only 16 mW from f2.5-V sponse). wpplies. Although requiring additional circuitry to provide for