(内存基本知识)_DRAM工作原理.ppt

DRAM工作原理 DRAM工作原理;Dynamic Random Access Memory Each cell is a capacitor + a transistor Very small size SRAM uses six transistors per cell Divided into banks, rows columns Each bank can be independently controlled;Main Memory Everything that happens in the computer is resident in main memory Capacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanoseconds Why DRAM for Main Memory ?? ?? Cost effective (small chip area than SRAM) ?? High Speed(than HDD, flash) ?? High Density(~Gbyte) ?? Mass Production ……;Notation: K, M, G ?? In standard scientific nomenclature, the metric modifiers K, M, and G to refer to factors of 1,000, 1,000,000 and 1,000,000,000 respectively. ?? Computer engineers have adopted K as the symbol for a factor of 1,024 (210 ) ?? K: 1,024 (210 ) ?? M: 1,048,576 (220 ) ?? G: 1,073,741,824 (230 ) ?? DRAM’ density ?? 256M-bit ?? 512M-bit;DRAM Density;What is a DRAM? ?? DRAM stands for Dynamic Random Access Memory. ?? Random access refers to the ability to access any of the information within the DRAM in random order. ?? Dynamic refers to temporary or transient data storage. Data stored in dynamic memories naturally decays over time. Therefore, DRAM need periodic refresh operation to prevent data loss.;Memory: DRAM position ?? Semiconductor memory device ?? ROM: Non volatile ?? Mask ROM ?? EPROM ?? EEPROM ?? Flash ?? NAND: low speed, high density ?? NOR: high speed, low density ?? RAM: Volatile ?? DRAM: Dynamic Random Access Memory ?? SRAM: Static Random Access Memory ?? Pseudo SRAM;DRAM Trend : Future ?? High Speed - DDR(333MHz~500MHz), DDR2(533~800Mbps), DDR3(800~1600Mbps) - Skew-delay minimized circuit/logic : post-charge logic, wave-pipelining - New Architecture : multi-bank structure, high speed Interface ?? Low Power - 5.5V = 3.3V(sdr) = 2.5V(ddr) = 1.8V(ddr2) = 1.5v (ddr3) = 1.2v? - Small voltage swing I/O interface : LVTTL to SSTL, open drain - Low Power DRAM(PASR, TCSR, DPD) ?? High Density - Memory