一款高电源抑制比低压差线性稳压器设计.pdfVIP

A b stra ct W ith the popu larity of hand-held electronic com m un ication dev ices, especially tab let P C s and sm art phones in recent years, the m arket of p ow er m anagem ent ch ip is grow ing. A ccording to industry research firm IH S iSupp li, revenue in 20 11 from pow er m anagem ent sem iconductors is expected to reach $33.1 b illion . In the m arket of pow er m anagem ent ch ip , the proportion of low dropout linear regu lator (L ow D ropout R egu lator, LD O ) is about 10% . W ith the decline in ch ip supp ly voltage, the sensitiv ity of the ch ip pow er supp ly ripp le is greatly im proved. So w e need h igh P SR (Pow er Supp ly R ejection ，P SR ) p ow ers. T he characteristics of h igh P SR L D O really fit th is requ irem ent, therefore，this thesis designed a low dropout linear regulator w ith m ax im um output current 150m A and h igh P SR . F irst, the thesis discusses the im p lem entations of the h igh pow er supp ly rejection L D O . A nalyzes the pow er supp ly rejection characteristics of the single-stage pow er transistor L D O in the w ho le frequency range, and lists several pub lished L D O circuit structures w ith h igh pow er supp ly rejection . T hen ，the thesis analyzes the L D O loop com pen sation m ethods, and discu sses the pros and con s of several com pensation m ethods. F inally, a h igh pow er supp ly rejection ratio L D O w as im p lem ented w ith U M C , 0.5 a(m LV T C M O S process. T he input voltage of the L D O is from 2.5V to 5.5V , and the output voltage is 2V to 3.6V , w ith the m ax im um load current of 150m A . The sim u lation s of the circu it at all process corners, different tem p erature and voltage， sh o w th at th e P S R o f th is L D O is le ss th an -8 0 d B a t 10 k H z an d is le ss th a n -4 0 d B In the w hole frequency range. K eyw ords :L ow D ropout R egu lato