7-A Multistage Amplifier Technique with英文学习资料 .pdfVIP

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 339 A Multistage Amplifier Technique with Embedded Frequency Compensation Hiok-Tiaq Ng, Student Member, IEEE, Ramsin M. Ziazadeh, Student Member, IEEE, and David J. Allstot, Fellow, IEEE Abstract— A new multistage operational amplifier topology power-supply voltage is reduced by the scaling factor , then requires only NNN 2 embedded compensation networks for NNN gain stages. The compensation circuits do not load the output stage, DNR constant and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low- (1) power resistance–capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-m n-well CMOS process, a Bandwidth constant (2) single-ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/s average slew rate with 40 pF load. Index Terms— Frequency compensation, multistage amplifiers, (3) operations amplifier design. Therefore, both and must be increased by to maintain I. INTRODUCTION constant dynamic range and constant bandwidth, respectively.