Quartus中的延时分析.pptVIP

Timing Analysis in Quartus Features Quartus is capable of doing single clock design timing analysis and multi-clock design timing analysis Single clock timing analysis Fmax (maximum clocking frequency) Tsu, Th, Tco (setup time, hold time, clock-to-out time) Slack analysis for Fmax (incl. delays to/from pins) Multi-clock analysis Allows user to analyze timing for a design containing register-to-register paths which are controlled by different clocks Slack analysis is used Combinatorial Loop Detection Quartus automatically detects combinatorial loops Features Different types of timing information (Refer to the compilation section for more information) Timing without place route Timing with place route A mix of both for a hierarchical design By default, timing analysis is performed automatically after compilation Can be disabled Timing information can be exported to other EDA tools via VHDL, Verilog and Standard Delay File (SDF) In This Section Timing analysis for a single clock system Register Performance Setup Time Hold Time Clock-to-Out Making Timing Assignments Timing analysis of a multi-clock system How to make multi-cycle assignments Timing Wizard Compile Design Reporting Timing Results Timing information is part of the Compilation Report Summary Timing Analyses fmax (not incl. delays to/from pins) or fmax (incl. delays to/from pins) Register-to-Register Table tsu (Input Setup Times) th (Input Hold Times) tco (Clock to Out Delays) tpd (Pin to Pin Delays) All timing results are reported here fmax (not incl. delays to/from pins) fmax Analysis fmax Analysis fmax Analysis fmax Analysis fmax Analysis Carry Chain in Data Delay Path Locate Delay Path in Floorplan Locate Delay Path in Floorplan Fmax (incl. delays to/from pins) Input Pin Period External Input Delay Output Pin Period External Output Delay Fmax (incl. delays to/from pins) Setting External Input/Output Delay Setting External Input/Output Delay Setup Time Analysis Setup Time Analysis thold Analysi