集成电路设计-10-系统设计-3.pptVIP

EIS-Wuhan University 集成电路设计 第10章 系统设计（3）-设计方法学 Design Methodologies 纲要 概述 实现方法 基于单元的设计 基于阵列的设计 1.概述 ——The Design Productivity Challenge A Simple Processor A System-on-a-Chip: Example Design Entry for VLSI System 2.实现方法Implementation Choices The Custom Approach Transition to Automation and Regular Structures 3.基于单元的设计 Cell-based Design (or standard cells) Standard Cell — Example Standard Cell – The New Generation Standard Cell - Example PLA- Programble Logic Array Two-Level Logic PLA Layout – Exploiting Regularity MacroModules 复杂性超过单元库中单元的程度 Megacell（巨单元） Hard—具有指定功能，及预先确定的物理设计。 Soft —具有指定功能，但无预先确定的物理设计。 hard-macro Modules “Soft” MacroModules Inside the 22v10 “Macrocell” Block Outputs may be registered or combinational, positive or inverted ?? Registered output may be fed back to AND array for FSMs, etc. Input/Output Equivalent Schematics “Intellectual Property” 4. Semicustom（半定制 ）Design Flow 时序最终确定The “Design Closure(设计收敛)” Problem Integrating Synthesis with Physical Design 5.基于阵列的设计方法 预扩散（掩模）阵列 Gate Array （ Sea-of-gates） 门海Sea-of-gate Sea-of-gates 预布线阵列Prewired Arrays Based on Programming Technique 熔丝Fuse-based (program-once) 非易失EPROM RAM based Programmable Logic Style Array-Based 查找表Look-up Table Programmable Interconnect Style Channel-routing Mesh networks Fuse-Based FPGA Programmable Array Logic (PAL) Array-Based Programmable Logic Device（PLD） Programming a PROM More Complex PAL 可编程ASIC的基本资源 位于芯片中央的可编程功能单元 分布于芯片各处的可编程布线 位于芯片四周的可编程IO Logic Cell of Actel Fuse-Based FPGA Look-up Table Based Logic Cell LUT-Based Logic Cell Array-Based Programmable Wiring Mesh-based Interconnect Network Programming an Antifuse EPLD Altera MAX Altera MAX Interconnect Architecture Design at a crossroadSystem-on-a-Chip Architecture Reuse Reuse comes in generations Pre-diffused (Gate Arrays) Pre-wired (FPGAs) Array-based 编程前 V DD GND polysilicon metal possible contact 编程后 (4-input NOR) In 1 In 2 In 3 In 4 Out 几何隔离oxide-isolation 栅隔离gate-isolation 无布线通道 Primitive C