第四章vhdl设计初步.pptVIP

方法一：根据电路原理图 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder1 IS PORT (a,b:IN STD_LOGIC; co,so:OUT STD_LOGIC); END h_adder1; ARCHITECTURE fh1 OF h_adder1 IS BEGIN so=NOT(a XOR (NOT b)); co=a AND b; END fh1; 并行赋值语句 方法二：根据真值表 … ARCHITECTURE fh2 OF h_adder2 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel=ab; PROCESS(sel) BEGIN CASE sel IS WHEN 00=so=0;co=0; WHEN 01=so=1;co=0; WHEN 10=so=1;co=0; WHEN 11=so=1;co=1; WHEN OTHERS=NULL; END CASE; END PROCESS; END fh2; 并置操作符 完整条件语句 全加器 或门描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL