第6章 组合逻辑设计实践 2.ppt

* chapter 6 * Class exercise A B C D F D’ A A’ D C’ D’ C’ A B Judge whether the following circuit has static hazard or not, if static hazard exist, please point it and eliminate by using K-map. Then write the hazardless minimal sum. * chapter 6 * 6.10 Adders、Subtractors and ALU Used to do binary addition and subtraction 1. Half adders and full adders （1）half adders X Y HS CO 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 half sum：HS=X⊕Y carry-out：CO=X·Y X Y HS CO * chapter 6 * （2）full adders CIN X Y S CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 sum：S=X⊕Y⊕CIN carry：CO=X·Y+CIN·X+CIN·Y * chapter 6 * 2、ripple adders Use 1-bit full adder as a module to construct n-bit ripple adder. X Y CIN CO S X0 Y0 S0 C0 C1 X Y CIN CO S X1 Y1 S1 X Y CO S Xn-1 Yn-1 Sn-1 C2 Cn … 电路简单，扩展方便，但运算速度慢 * chapter 6 * 3、carry-lookahead adders Parallel adders issues：how to get the carry information early? solution： carry-lookahead （1）definition： ①carry generating variable：gi=xi·yi ②carry propagating variable：pi=xi+yi ③the Ci+1 carry-out：Ci+1=gi+pi·Ci * chapter 6 * Ci+1=gi+pi·(gi-1+pi-1·(…(g0+p0·C0) …) C0=0， Ci is relative to addends only and just three level delay, which to reduce the computation time. （2）structure Si=Xi⊕Yi⊕Ci Ci+1=gi+pi·Ci 先行进 位逻辑 Si Xi Xi-1 X0 Yi Yi-1 Y0 … … Ci C0 两级与或式 * chapter 6 * （3）MSI adders 74×283，4-bit carry-lookahead adders 加法器的级联（P.482图6-89） * chapter 6 * 4、subtractor Full subtractor D=X⊕Y⊕BIN BO=BIN·Y+BIN·X’+X’·Y BIN X Y D BO 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 X Y BO D BIN * chapter 6 * In algorithm, subtraction can be operated by using addition. X-Y= X+(Y)2’s= X+(Y)1s’+1 So circuit can be manipulated： D=X⊕Y’⊕BIN’ BO=(BIN’X+BIN’Y’ +XY’)’ D BIN BO subtractor * chapter 6 * 5、MSI arithmetic and logic units perform a number of different arithmetic and logical operations. ALU A B F SEL M CIN CO G P A=B * chapter 6 * 卡诺图的降维 卡诺图降次的过程： 设m=n+1，在m-变量函数F(X1,X2,…,Xn,Xn+1