fpga常用程序例子.docVIP

或门的描述 LIBRARY IEEE; USE IEEE.STD LOGIC 1164.ALL ENTITY orl IS PORT( a,b: INSTD.LOGIC; y: OUT STD LOGIC); END orl; ARCHITECTURE example 1 OF orl IS BEGIN y=a OR b; END example 1; 半加器的描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT(a,b:IN STD_LOGIC; so,co:OUT STD_LOGIC); END h_adder; ARCHITECTURE example2 OF h.adder IS BEGIN so=a XOR b; co=a AND b; END example2; 2选1数据选择器的描述 LIBRARY IEEE； USE IEEE.STD LOGIC 1164.ALL ENTITY mux21 IS PORT( a,b: IN STD LOGIC; s: IN STD LOGIC; y: OUT STD LOGIC); END mux21; ARCHITECTURE example3 OF mux21 IS BEGIN y=a WHEN s=,0, ELSE b； END ARCHITE