非同步式计数器和运作.ppt

Chapter 9 Counters計數器 Asynchronous Counter Operation 非同步式計數器的運作 Synchronous Counter Operation 同步式計數器的運作 Up/Down Synchronous Counters 上 / 下數的同步式計數器 Design of Synchronous Counters 同步式計數器的設計 Cascaded Counters 串接計數器 Counter Decoding 計數器的解碼 Counter Applications 計數器的應用 Troubleshooting 檢修 Logical Symbols with Dependency Notation 具有相依註標的邏輯符號 Programmable Logic 可程式邏輯 Digital System Application 數位系統的應用 Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK. Figure 9--1 A 2-bit asynchronous binary counter. Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. Figure 9--5 Four-bit asynchronous binary counter and its timing diagram. Figure 9--6 An asynchronously clocked decade counter with asynchronous recycling. Figure 9--7 Asynchronously clocked modulus-12 counter with asynchronous recycling. FigureA--21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.) Figure A--22 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.) Figure A-23 74LS93A connected as a modulus-12 counter. A 2-bit synchronous binary counter. Figure 9--9 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal). Figure 9--11 A 3-bit synchronous binary counter. Figure 9--13 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas. Figure 9--14 A synchronous BCD decade counter.. Figure A--24 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.) Figure A--25 Timing example for a 74HC163. Figure A--26 The 74LS160 synchronous BCD