systemverilog硬件设计及建模.pptxVIP

新操作符 改进的for循环 新的do … while底部检测循环 新的foreach循环;7.1 新操作符;7.1.1 递增递减操作符;7.1.1递增递减操作符;7.1.2 赋值操作符;7.1.2 赋值操作符;7.1.2 赋值操作符;7.1.3 有无关通配符的相等操作符;7.1.3 有无关通配符的相等操作符;7.1.4 设置成员操作符—inside;7.2 操作数改进;7.3 改进的for循环;7.4 底部检测的do ... while循环;always @ * begin begin : loop integer i; first_bit = 0; for (i = 0; i = 63; i = i + 1) begin : pass if ( i start_range) disable pass; //继续循环 if ( i end_range) disable loop; //跳出循环 if ( data[i]) begin first_bit = i; disable loop; //跳出循环 end end //for end //loop end //always;//disable在任务所有语句执行完成前提前从任务中返回 task add_up_to_mux( input [5 : 0] max, output [63 : 0] result); integer i begin result = 1; if (max == 0) disable add_up_to_mux; for ( i = 1; i = 63; i = i + 1) begin result = result + result; if (i == max) disable add_up_to_max; end end endtask;continue语句： logic [15 : 0] array [0 : 255]; always_comb begin for (int i = 0; i = 255; i ++) begin : loop if (array [i] == 0) continue; //下一i transform_function(array[i]); end //for end;return语句： task add_up_to_max (input [5 : 0] max, output [63 : 0] result); result = 1; if (max == 0) return; //退出任务 for ( int i = 1; i = 63; i = i + 1; begin result = result + result; if (i == max) return; end endtask;always_ff @(posedge clock, posedge reset) begin : FSM_procedure logic breakVar; if (reset) begin : reset_logic … end : reset_logic else begin : FSM_sequencer unique case (SquatState) wait_rx_valid : begin :rx_valid_state Rxready = ‘1; breakVar = 1; for (int j = 0; j NumRx; j += 1) begin : loop1 for (int i = 0; i NumRx; i += 1) begin : loop2 if Rxvalid[i] RoundRobin[