基于USB3.0 IP的数字模块后端研究实现.docVIP

硕士学位论文 基于USB3.0IP的数字模块后端研究实现 作者姓名： 指导教师: 学位类别: 工程硕士 学科专业: 电子与通信工程 研究所 : 二零一七年八月 The Backend Digital Block Research and Implementation Based on IP of USB3.0 In partial fulfillment of the requirement For the degree of Master of Electronics and Communication Engineering August, 2017 ：摘 要 目前随着芯片功能越发的强大，集成度也随之增大。为加快芯片的设计速度，减小设计周期，集成通用的IP（Intellectual Property）是现在很主流的设计方法。随着USB（Universal Serial Bus）技术的广泛应用，在SoC（System on Chip）中集成USB功能也是必然趋势。 论文拟以集成USB3.0 IP为研究对象，进行相关后端设计及相关实验研究，具体如下： （1）以SoC集成USB 3.0 IP为切入点，研究基于USB 3.0 IP的数字后端设计方法，并确定最终的后端设计方案； （2）基于SoC 集成 USB 3.0 IP，研究低功耗设计方法，并选择适当的方法应用在实际设计当中； （3）基于SoC集成USB 3.0 IP，研究后端布局及电源线规划策略；从而通过优化芯片布局，来优化芯片时序、绕线资源、减少芯片面积；优化电源线策略，来降低电源线的电压降、降低功耗； （4）基于SoC集成USB 3.0 IP，研究时钟树综合方法；从而实现时钟树延时减小、时钟树偏差减小，降低对时序的影响； （5）基于SoC集成USB 3.0 IP，进行后端设计验证以及芯片USB功能测试。通过后端设计验证从设计的角度保证正确性；通过芯片测试从功能的角度保证正确性。 本文通过实际项目来验证多种低功耗设计方法的可行性，完成实际项目，测试验证项目的设计正确性。 关键词：数字后端，USB 3.0 IP，低功耗，SOC，时钟树综合Abstract At present, the chip function is more and more powerful, the integration is getting higher and higher. in order to speed up the design speed of chip , reduce the design cycle, integrated general IP (Intellectual Property) is now a mainstream design method.As the USB (Universal Serial Bus) technology is widely used, in the SoC (System on Chip) integrated USB function is also inevitable trend. This thesis intends to integrate USB3.0 IP as the research object, carry out the relevant back-end design and related experimental research, as follows: Based on USB 3.0IP as the entry point, this thesis studies the digital back-end design method based on USB 3.0 IP and determines the final back-end design scheme; Based on SoC integrated USB 3.0 IP, research low power design method, and select the appropriate method applied in the actual design; Based on SoC integrated USB 3.0 IP, research floorplan and power plan strategy; by optimizing the chip floorplan, to optimize the chip timing, winding resources, reduce the chip area; optimize the power plan strategy to reduce the power