数字逻辑设计及运用 4-3卡诺图.pptVIP

class-exercises 1、write the complement of the function Y. Y=A（B’+C）+（A+C）’ 2、 write the duality of the function F. F=A（B+C’）+（A+C ’ ）’ 3、which kind of gate under the nagitive-logic equal to the NAND gate under the positive –logic? class-exercises 1. If ， , what is the relation between the fonction F and fonction G, complement or duality? 2. (Hamlet circuit.) Complete the timing diagram and explain the function of the circuit in Figure X4.78. Where does the circuit get its name? (P236-4.61) class-exercises 2. (Hamlet circuit.) Complete the timing diagram and explain the function of the circuit in Figure X4.78. Where does the circuit get its name? (P236-4.61) 4.3.3 Combinational Circuit Minimization (组合电路的化简) What is the Minimization? (什么是最简?) Formula Minimization (公式法化简) Karnaugh Maps (卡诺图化简) minimization methods (P211) The minimization methods reduce the cost of a two-level AND-OR, OR-AND, NAND-NAND, or NOR-NOR circuit in three ways: 1. By minimizing the number of first-level gates. 2. By minimizing the number of inputs on each first-level gate. 3. By minimizing the number of inputs on the second-level gate. ExampleF = ∑N3,N2,N1,N0(1, 2, 3, 5, 7, 11, 13) ExampleF = ∑N3,N2,N1,N0(1, 2, 3, 5, 7, 11, 13) Notes (P211) if two product or sum terms differ only in the complementing or not of one variable, we can combine them into a single term with one less variable. So we save one gate and the remaining gate has one fewer input. WHY MINIMIZE? Minimization is an important step in both ASIC design and in design PLDs. Extra gates and gate inputs require more area in an ASIC chip, and thereby increase cost .The number of gates in a PLD is fixed, so you might think that extra gates are free—and they are, until you run out of them and have to upgrade to a bigger, slower, more expe