如何读懂时序图.docVIP

/itangcle CPE/EE 421 Microcomputers WEEK #10 Interpreting the Timing Diagram 如何读懂时序图 The 68000 Read Cycle 2 Timing Diagram of a Simple Flip-Flop Idealized form of the timing diagram Actual behavior of a D flip-flop Data hold time Data setup time Max time for output to become valid after clock General form of the timing diagram An alternative form of the timing diagram The Clock ? A microprocessor requires a clock that provides a stream of timing pulses to control its internal operations 一个微处理器需要时钟,提供一系列的计时脉冲来控制 它的内部操作 ? A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7 一个 6800 芯片的储存器最小能过接收 8 个从 S0 到 S7 的时钟脉冲. A memory access begins in clock state S0 and ends in state S7 6 The most important parameter of the clock is the duration of a cycle, tCYC. 7 8 Address Timing 地址时序 ? We are interested in when the 68000 generates a new address for use in the current memory access 我们感兴趣的是当 6800 芯片能够生成一个 新的地址供当前的内存访问 ? The next slide shows the relationship between the new address and the state of the 68000 ’s clock 下面展示的是新的地址跟 6800 芯片时钟的 关系 1: S0 在没有初始化的时候，地址总 线总是包涵新的地址。 2： S1 这个状态说明一个新的地址可 以供内存访问 Address Timing 地址时序 ? Let’s look at the sequence of events that govern the timing of the address bus 让我们看看事件发生的顺序,管理时间的地址总线 ? The “old” address is removed in state S0 旧的地址已经从 S0 中移除 ? The address bus is floated for a short time, and the CPU puts out a new address in state S1 地址要先存在一小段时间后，CPU 才能把 心的地址状态写入 S1 中 12 The old address is removed in clock state S0 and the address bus floated 13 tCLAV The designer is interested in the point at which the address first becomes valid. This point is tCLAV seconds after the falling edge of S0. 我们感兴趣的是地址生效的那个时间点。这 个时间是在 S0 失效后，tCLAV 秒后。 Address and Address Strobe 地址跟地址选通 ? We are interested in the relationship between the time at which the address is valid and the time at which the address strobe, AS*, is asserted 我们感兴趣的事在地址总线能够访问时， 地址选通是否有效。 ? When AS* is active-low it indicates tha