静态时序分析基本原理和时序分析模型上课讲义.ppt

? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation ? 2009 Altera Corporation * ? 2009 Altera Corporation Quartus? II Software Design Series: Timing Analysis - Timing analysis basics * Objectives Display a complete understanding of timing analysis * How does timing verification work? Every device path in design must be analyzed with respect to timing specifications/requirements Catch timing-related errors faster and easier than gate-level simulation & board testing Designer must enter timing requirements & exceptions Used to guide fitter during placement & routing Used to compare against actual results ? ? IN CLK OUT D Q CLR PRE D Q CLR PRE combinational delays ? CLR * Path & Analysis Types Three types of Paths: Clock Paths Data Path Asynchronous Paths* Clock Paths Async Path Data Path Async Path D Q CLR PRE D Q CLR PRE Two types of Analysis: Synchronous – clock & data paths Asynchronous* – clock & async paths *Asynchronous refers to signals feeding the asynchronous control ports of the registers * Launch & Latch Edges CLK Launch Edge Latch Edge Data Valid DATA Launch Edge: the edge which “launches” the data from source register Latch Edge: the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle) * Setup & Hold Setup: The minimum time data signal must be stable BEFORE clock edge Hold: The minimum time data signal must be stable AFTER clock edge D Q CLR PRE CLK Th Valid DATA Tsu CLK DATA Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable. * Data Arrival Time Data Arrival Time = launch edge + Tclk1 + Tco +Tdata CLK REG1.CLK Tclk1 Data Valid REG2.D Tdata Launch Edge Data Vali