VHDL独立按键扫描.pdfVIP

. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity key is port(A,B,C,D:in std_logic;-- 键盘模块的四个外接按键，编号依次是 A、 B、C、D clk_key:in std_logic;-- 时钟信号，作为消抖计时 key_value:out std_logic_vector(1 downto 0);-- 输出按键值 out_clk:out std_logic:=0-- 键值传送脉冲信号，宽度为 8 个时钟信号周期 _| |____ ); end entity; architecture art of key is signal key_value_1:std_logic_vector(1 downto 0); signal abcd:std_logic_vector(3 downto 0); begin abcd=ABCD; process(clk_key) variable counter: std_logic_vector(15 downto 0); variable state:integer range 4 downto 0; begin if rising_edge(clk_key)then case state is when 0 = if (abcd(0)=0 or abcd(1)=0 or abcd(2)=0or abcd(3)=0) then state:=1; else state:=0; end if; when 1 = if counter=1111111111111110 then state:=2; counter:=0000000000000000; else counter:=counter+1; state:=1; end if; when 2 = if abcd(0)=0 or abcd(1)=0 or abcd(2)=0or abcd(3)=0 then case abcd is when 0111=key_value_1=00;state:=3; when 1011=key_value_1=01;state:=3; when 1101=key_value_1=10;state:=3;