基于FPGA的数字秒表设计.docVIP

基于FPGA数字秒表设计 摘要：该设计是用于体育比赛数字秒表,基于FPGA在Quartus II 9.0sp2软件下应用VHDL语言编写程序,采取ALTRA企业CycloneII系列EP2C8Q208芯片进行了计算机仿真，并给出了对应仿真结果。本设计有效克服了传统数字秒表缺点采取EDA技术采取自上而下设计思绪。绘制出了具体逻辑电路，最终又经过硬件上对其进行调试和验证。该电路能够实现很好计时功效,计时精度高，最长计时时间可达一个小时。  关键字：数字秒表；EDA；FPGA；VHDL；Quartus II The design of digital stop watch based on FPGA Abstract：This design is a digital stop watch which is used for athletic contests and is based on FPGA using VHDL language to write program in Quartus II software,adopting EP2C8Q208 chip of CycloneII series of ALTRA company for computer simulation and at the same time showing the corresponding